The present invention relates generally to the field of electronics. More particularly, the present invention relates to a power MOS transistor device and methods of manufacturing the same. Merely by way of example, the invention has been applied to a power MOS transistor incorporating fixed charges that balance the charge in the drift region. The present invention has applicability to both lateral and vertical MOSFET structures as well as other MOS structures.
Power MOSFETs are widely used as switching devices in many electronic applications. In order to minimize conduction and switching power loss it is desirable that power MOSFETs for a given breakdown voltage have low specific on-resistance and capacitances. Specific on-resistance (Rsp) is defined as the on-resistance area product (Ron* A). The Superjunction (SJ) structure achieves a low specific on-resistance by paralleling higher doping alternate p-type and n-type layers or pillars that are charge balanced. Therefore, for a SJ structure, it is desirable to pack as many pillars or cells in a given unit area to lower Rsp.
In a SJ structure, the minimum widths of the n-type and p-type pillars set a limitation on reducing cell pitch and scaling the device. There are also several drawbacks related to manufacturing this structure, including the need to grow multiple epitaxial layers combined by successive implant and diffusion steps. Alternative approaches such as forming trenches followed by epitaxial trench filling or providing floating islands have similar disadvantages. Therefore, there is a need in the art for a power MOS transistor characterized by a low Rsp and low capacitances that can be scaled to finer cell pitches. Additionally, reductions in manufacturing complexity are desirable.